- ARM abbreviations is Advance Risk Processor
- ARM has three different platforms: A- Mobile Platform, R-Automobile Platform, M-Embedded Platform
ARM Cortex R – Modes
| Mode | Encoding value in Registers (Binary) | Description |
|---|---|---|
| User (USR) | 10000 | Unprivileged mode in which most applications run |
| FIQ | 10001 | Switch to FIQ mode |
| IRQ | 10010 | Switch to IRQ mode |
| Supervisor (SVC) | 10011 | After reset, the CPU is in the Supervisor mode |
| Monitor (MON) | 10110 | Implemented with Security Extensions |
| Abort (ABT) | 10111 | Switch to Abort mode |
| Hyp (HYP) | 11010 | Implemented with Virtualization Extensions |
| Undefined Instruction (UND) | 11011 | Switch to Undefined Instruction Mode |
| System Mode ( Shares User Mode registers ) | 11111 | Switch to System Mode ( Shares User Mode registers ) |
Exception Handler
Exception
if you have the question like what is exception or exception Handler? here your Answerer
- An “Exception” is an event that makes the processor temporarily halt the normal flow of program execution, for example, to service an interrupt from a peripheral.
- Before attempting to handle an exception, the processor preserves the critical parts of the current processor state so that the original program can resume when the handler routine has finished.
| Mode Function | Privilege | |
|---|---|---|
| User (USR) | The mode in which most programs and applications run Unprivileged | Unprivileged |
| FIQ | Entered on an FIQ interrupt exception | Privileged |
| IRQ | Entered on an IRQ interrupt exception | Privileged |
| Supervisor (SVC) | Entered on reset or when a Supervisor Call instruction (SVC) is executed | Privileged |
| Abort (ABT) | Entered on a memory access exception | Privileged |
| Undef (UND) | Entered when an undefined instruction executed | Privileged |
| System (SYS) | The mode in which the OS runs, sharing the register view with User mode | Privileged |
Reset
Occurs when the processor reset pin is asserted
- For signaling Power-up
- For resetting as if the processor has just powered up
Undefined instruction
Occurs when the processor or coprocessors cannot recognize the current execution instruction.
Software Interrupt (SWI)
- User-defined interrupt instruction
- Allow a program running in User mode to request privileged operations that are in Supervisor mode.
- For example, RTOS functions
Prefetch Abort
- Fetch the instruction from an illegal address, the instruction is flagged as invalid.
- However, instructions already in the pipeline continue to execute until the invalid instruction is reached and then a Prefetch Abort is generated.
- All prefetch aborts are precise aborts.
When a Prefetch Abort (PABT) occurs, the processor marks the prefetched instruction as invalid but does not take the exception until the instruction is to be executed. If the instruction is not executed because a branch occurs while it is in the pipeline, the abort does not occur.
Data Aborts
- A data transfer instruction attempts to load or store data at an illegal address
An error occurring on a data memory access can generate a data abort. If the instruction generating the memory access is not executed, for example, because it fails its condition codes, or is interrupted, the data abort does not take place. A Data Abort (DABT) can be either precise or imprecise, depending on the type of fault that caused it.
IRQ
The processor external interrupt request pin is asserted (LOW) and the I bit in the CPSR is clear (enable)
FIQ
The processor external fast interrupt request pin is asserted (LOW) and the F bit in the CPSR is clear (enable)
Interrupt Priority
- Priority 1 — Highest
- Priority 2 — Second highest
- The interrupt with higher priority is always serviced first.
NVIC, VIC, IVT
- NVIC allows nesting based on priority — high-priority interrupts can pre-empt lower-priority ones.
- VIC executes one interrupt at a time in order of occurrence — no nesting.
- IVT just holds the addresses of all interrupt service routines — actual servicing is handled by the interrupt controller.
NVIC (Nested Vectored Interrupt Controller)
| Condition | Action |
|---|---|
| X & Y occur at the same time | X is serviced first; Y is put on hold |
| Y is already being serviced and X occurs | Interrupt Y is paused; X is serviced immediately; resume Y after X finishes |
| Processing mode | Nested — higher-priority interrupts can pre-empt lower-priority ones |
VIC (Vectored Interrupt Controller)
| Condition | Action |
|---|---|
| X & Y occur at the same time | X is serviced first; Y waits |
| Y is already being serviced and X occurs | Y continues to completion; X is handled afterwards |
| Processing mode | Non-nested — current interrupt must finish before the next one starts |
IVT (Interrupt Vector Table)
| Feature | Description |
|---|---|
| What it contains | Table of addresses (pointers) to each interrupt’s handler |
| Role | When an interrupt occurs, the PC jumps to the handler address from IVT |
| Earlier usage | VIC was sometimes referred to as IVT because it simply provided addresses; priority handling was not part of IVT itself |
