TMS570LC4357

• TMS570LC4357 is High-Performance Automotive-Grade Micro controller for Safety-Critical Applications
• TMS570LC43x family is based on the ARM® Cortex®-R5F core  32-Bit RISC CPU
• Its a Big Endian MCU (Ex: Data is 22,33,44,55 then address Data[0]=22, Data[1]=33, Data[2]=44, Data=55)
• Difference between TMS570LCXX and TMS570LSXXX ? LS – Lockstep and LC – Lockstep with Cache.

Abbreviations

• MMR – Memory Mapped Register.
• IOMM – I/O Multiplexing Module.
• VIM – Vectored Interrupt Manager.
• ECC – Error Code Correction
• ISR – Interrupt Service Routine
• SWI – Software Interrupt
• IRQ – Interrupt Request
• FIQ – Fast Interrupt Request
• FEE – Flash EEPROM Emulation)
• HCG – Hardware Abstraction Layer Code Generator

Feature

Parameter	Specification
CPU	ARM® Cortex®-R5F core
Package	337 BGA
Frequency (MHz)	300
Cache (KB)	32 I, 32 D
Flash Memory	4096 KB
RAM	512 KB
Data Flash EEPROM	128 KB
GPIO	168
EMAC	10/100
FlexRay	2-ch
CAN	4
MibADC 12-bit (Ch)	2 (41 ch)
N2HET (Ch)	2 (64)
ePWM Channels	14
eCAP Channels	6
eQEP Channels	2
MibSPI (CS)	5 (4 × 6 + 2) Difference between MibSPI and SPI? : Refer Here
SPI (CS)	–
SCI (LIN)	4 (2 with LIN)
I2C	2
GPIO (INT)	168 (with 16 interrupt capable)
EMIF	16-bit data
ETM (Trace)	32-bit
RTP/DMM	6/16
Operating Temperature	–40ºC to 125ºC
Core Supply (V)	1.14 V – 1.32 V
I/O Supply (V)	3.0 V – 3.6 V
Rating	Automotive

I/0, Interrupts, Timer,

Interrupt

TMS570 has 2 interrupts, Normal Interrupt request (IRQ) and Fast Interrupt Request (FIQ).

• How to use the interrupts of GIO?

• The LC4357 does not use the PL19x IP. It uses the TI VIM module which is described in the device TRM. Reference : www.ti.com/…/spnu563

Phantom Interrupts

A phantom interrupt is an interrupt that the CPU cannot identify the source. When a phantom interrupt occurs, the CPU internal nIRQ or nFIQ request signal is low but the contents in the VIM interrupt offset register (IRQIVEC/FIQIVEC) and interrupt request register (INTREQ) stay at zero. It is undesirable because it not only adds a lot overhead in the processing but also would lead to unexpected behavior in the system operation. It could be caused by improper handling of a legitimate interrupt. Reference : http://www.ti.com/lit/an/spna218/spna218.pdf

I/O Multiplexing Module (IOMM)

• The IOMM contains memory-mapped registers (MMR) that control device-specific multiplexed functions.
• The safety and diagnostic features of the IOMM are:
  • Kicker mechanism to protect the MMRs from accidental writes
  • Error indication for access violations

PINMMR – PIN Multiplexing Module Register.

• Reference :
• Refer : Page number 47 : “4.2.2 Multiplexing” of data sheet : “spns195c.pdf“
• Refer : Page number 301 : “6 I/O Multiplexing and Control Module (IOMM)” of data sheet : “spnu563.pdf“
• Multiplexing Input and Output  : https://www.mbeckler.org/coursework/2005-2006/ee2361lab4.pdf

nError Pin in TMS570LC43570 (ESM Module)

The Error Signaling Module (ESM) monitors on-chip device errors and determines whether an interrupt or external Error pin/ball (nERROR) is triggered when a fault is detected. The nERROR signal can be monitored externally as an indicator of a fault condition in the microcontroller.

Real Time Interrupt (RTI)

• The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code.
• The RTI module uses the RTI1CLK clock domain for generating the RTI time bases
• In addition the RTI provides a mechanism to synchronize the operating system to the FlexRay communication cycle.

Features

• Two independent 64-bit counter blocks
• Four configurable compares for generating operating system ticks or DMA requests. Each event can be driven by either counter block 0 or counter block 1.
• One counter block usable for application synchronization to FlexRay network including clock supervision 
• Fast enabling/disabling of events
• Two timestamp (capture) functions for system or peripheral interrupts, one for each counter block

RTI Functions

• Counter Operation
• Counter and capture Read Consistency
• Interrupt/DMA Request
• RTI Clocking
• Synchronizing Timer Events to Network Time (NTU)
• Detecting Clock Edges
• Switching from Internal Source to External Source
• Switching from External Source to Internal Source
• Digital Watchdog (DWD)

Reference

• Refer : Page number 127, data sheet : “spns195c.pdf“
• Refer : Page number 583, data sheet : “spnu563.pdf“

Enhanced High-End Timer (N2HET)

• The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
• The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port.
• The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O.
• Feature
  • Programmable timer for input and output timing functions
  • Reduced instruction set (30 instructions) for dedicated time and angle functions
    • The angle between hour and minute hand in 4:20 is 10 degrees. For a minute, the hour hand rotates by 30/60 = 1/2 degrees. hence, for 20 minutes it rotates by an angle of 20*1/2 = 10 degrees
• 256 words of instruction RAM protected by parity
• User defined number of 25-bit virtual counters for timer, event counters and angle counters
• 7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual counters
• Up to 32 pins usable for input signal measurements or output signal generation.
  • N2HET1[0] to N2HET1[31], N2HET2[0] to N2HET2[31],
  • Pin D8 (N2HET2[1]/N2HET1_NDIS) – N2HET1 Disable,
  • Pin D7 (N2HET2[2]/N2HET2_NDIS) – N2HET2 Disable
• Programmable suppression filter for each input pin with adjustable limiting frequency
• Low CPU overhead and interrupt load
• Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU) or DMA
• Diagnostic capabilities with different loopback mechanisms and pin status readback functionality

Functions

• Specialized Timer Micromachine
• N2HET RAM Organization
• Time Base
• Host Interface
• Interrupts and Exceptions
• Hardware Priority Scheme
• N2HET Requests to DMA and HTU

Reference

• Refer : Page number 180, data sheet : “spns195c.pdf“
• Refer : Page number 953, data sheet : “spnu563.pdf“

High-End Timer Transfer Unit (HET-TU)

The HTU is a dedicated transfer unit for the New Enhanced High-End Timer module. The HTU has a native interface to the N2HET RAM, and is used to transfer data to / from the N2HET RAM from / to another region in the device memory-map. There is one HTU per N2HET module, so that there are 2 HTU modules on the device. The HTUx are bus masters in this device.

Feature

• CPU and DMA independent
• Master Port to access system memory
• 8 control packets supporting dual buffer configuration
• Control packet information is stored in RAM protected by parity
• Event synchronization (HET transfer requests)
• Supports 32 or 64 bit transactions
• Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64bit)
• One shot, circular and auto switch buffer transfer modes
• Request lost detection

Functions

• Data Transfers between Main RAM and N2HET RAM
• Arbitration of HTU Elements and Frames
• Conditions for Frame Transfer Interruption
• HTU Overload and Request Lost Detection
• Memory Protection
• Control Packet RAM Parity Checking

Reference

• Refer : Page number 184, data sheet : “spns195c.pdf“
• Refer : Page number 1131, data sheet : “spnu563.pdf“

Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the reference clock (for counter 0) and VCLK as the “clock under test” (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

Memory

• Flash Bank 0      – 0x0000000.
• Flash Bank 1      – 0x0020000.
• RAM                  – 0x08000000.

Flash EEPROM Emulation TMS570LC43X (FFE)

• Memory 4MB of Program Flash With ECC (32 Sectors)
• Bank 0 – 2MB (16 Sectors)
• Bank 1 – 2MB (16 Sectors)
• 512KB of RAM With ECC
• 128KB of Data Flash for Emulated EEPROM with ECC (32 Sectors, each 4KB Segment).
• L2FMC – Level 2 Flash Module Controller.
• FEE(Flash EEPROM Emulation) is a software driver used to read/write/erase data in Flash memory
• For any system using Flash memory, the worst-case scenario includes a system failure, crash or power outage, while the Flash is being erased or re-programmed.
• There are two slave ports (Flash_PortA and Flash_PortB) to access the flash memory consisting of three flash banks. The two ports allow two masters to access among the three banks in parallel. There are two 2Mbyte banks and one EEPROM bank. The EEPROM bank is a flash bank that is dedicated for use as an emulated EEPROM. This device supports 128KB of flash for emulated EEPROM.
• 128KB of Data Flash for Emulated EEPROM
• HALCoGen will generate TI-FEE driver device specific files and configurations file.
• The Texas Instruments Hercules™ ARM® Safety MCUs built using TI’s F021 Flash process typically have one bank of Flash for emulating electrically erasable programmable read-only memory (EEPROM). This Flash is protected by single error correction double error detection (SECDED) error correcting code (ECC) bits. There is an additional feature to allow fully erased (all 1’s) or fully programmed (all 0’s) to be valid values. This additional feature may compromise the integrity of the SECDED scheme. While the risk is small, it needs to be understood by the system designer
  • Steps
    • The User needs to decide the number of blocks required. Each block can be considered as an array.
    • Then user has to set Number of Blocks required

Features

• Read, program and erase with a single 3.3 V supply voltage
• Supports error detection and correction
• Single Error Correction and Double Error Detection (SECDED)
• Error Correction Code (ECC) is evaluated in the CPU.
• Address bits included in ECC calculation

ECC generation tool

The Hercules microcontroller family contains as part of the embedded flash module a circuit that provides, the capability to detect and correct memory faults. This Single bit Error Correction and Double bit Error Detection circuit (SECDED) needs 8 Error correction check bits for every 64 bit of data.

EEPROM Emulation Firmware

• Refer : http://processors.wiki.ti.com/index.php/TI_FEE
• http://www.ti.com/lit/ug/spnu501h/spnu501h.pdf
• http://www.ti.com/lit/an/spna148/spna148.pdf
• http://processors.wiki.ti.com/index.php/F021FlashApi

Memory Self-Test

• Memory Self-Test Global Control Register (MSTGCR) (Check Technical Reference)

CRC Module

The CRC controller is a hardware module that performs CRC (Cyclic Redundancy Check) to verify memory integrity. When memory contents are read into the CRC controller, it generates a signature that represents the data. The CRC controller calculates this signature and compares it against a predetermined good signature to detect errors.

The CRC controller supports two channels, allowing parallel CRC calculations on multiple memories, and it works with any memory system.

For best performance, use the CRC module with the on-chip DMA controller. The DMA controller offloads the CPU and supports Auto and Semi-CPU modes.

The polynomial used for the signature calculation is a fix 64-bit primitive polynomial. The polynomial can be represented by equation F(x) = x⁶⁴+ x⁴+ x³+ x+1 or Linear Feedback Shift Register (LFSR).

CRC module: three modes: Auto, Full CUP mode, Semi CPU Mode, In addition fourth mode is called software mode.

• Reference :  TI Documents : Using the CRC Module on Hercules™-Based Microcontrollers

Ethernet

This TMS570LC43 have one Ethernet communication interface channel.

Feature

• 10/100 Mbps Ethernet MAC (EMAC) in either half- or full-duplex mode              
• IEEE 802.3 Compliant (3.3-V I/O Only)
• Supports MII, RMII, and MDIO

OSI Layers

OSI Layer	Name	Common Protocols
7	Application	HTTP, FTP, SMTP, DNS, Telnet
6	Presentation
5	Session
4	Transport	TCP, SPx
3	Network	IP, IPx
2	Data Link	Ethernet
1	Physical

Ethernet Pins

Functions

• Initialization                                                                                                     
• EMAC Control Module
• MDIO Module
• Packet Receive Operation
• Packet Transmit Operation
• Receive and Transmit Latency
• Transfer Node Priority(FIFO)
• Reset Considerations
  • Software Reset Considerations
  • Hardware Reset Considerations
• Interrupt Support

for UDP (TMS570LCXX with LwIP)

• EMAC_LwIP_Main(emacAddress);
• #define IP4_ADDR(ipaddr, a,b,c,d)  – Set an IP address given by the four byte-parts

Autonegotiation is performed in the hdkif_link_setup() API, found in the /Build-TMS570lc43x/lwip-1.4.1/ports/hdk/netif/hdkif.c file. lwipInit API is called from the lwip_main.c file. In this API, the following statement is used for setting up the network interface:

netif_add(&hdkNetIF[instNum], &ip_addr, &net_mask, &gw_addr, &instNum, hdkif_init, ip_input)

In this process, the hdkif_init API is called, present in the hdkif.c file mentioned above. This API is responsible for actually initialising the Ethernet hardware including autonegotiation. Once this is done, DHCP init is performed using lwIP.

This demo is limited in its functionality, but if you want to do more, there’s an lwIP wiki here, which is quite helpful.

AES Encryption:

• Advanced Encryption Standard (AES)
• TMS570LC4357 Hercules does not have any hardware based security for Ethernet communication. For the other security mechanisms, it would be up to DCU – DFU Ethernet communication to implement these algorithms in software. The AES 128 passphrase will be implemented.
• Reference : http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/629943?RM57L843-longevity-of-RM57L843-ZWT-MCU
• Other Reference for learn & use AES Encryption : https://github.com/kokke/tiny-AES-c
• AES Online Tool : http://aes.online-domain-tools.com/

Key Types

• AES-128-Key: AES Key should be 16 Bytes
• AES-192-Key : AES Key should be 24 Bytes
• AES-256-Key : AES Key should be 32 Bytes

Mode

• Cipher Block Chaining (CBC) mode
• Counter (CTR) mod
• Electronic Code Book (ECB) mode
• Authenticated Encryption with Associated Data (AEAD) mode

Initialization Vector

Cryptographic function	Key lengths		Initialization vector lengths (all modes)
In bytes	In bits	In bytes	In bits	In byte
AES	16, 24 or 32	128, 192 or 256	16	128
DES	1 to 8 bytes	8 to 64	16	128
TRIPLEDES	1 to 24	8 to 192	16	128
BLOWFISH	1 to 56	8 to 448	16	128
BLOWFISH-compat	1 to 56	8 to 448	16	128
RIJNDAEL-256	1 to 32	8 to 256	64	512
R4	1 to 256	8 to 2048	–	–
SERPENT	1 to 32	8 to 256	32	256
TWOFISH	1 to 32	8 to 256	32	256

• Reference:  https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38a.pdf

FlexRay Interface

FlexRay Pins

• FRAYRX1
• FRAYRX2
• FRAYTX1/GIOA[2]
• FRAYTX2/GIOB[0]
• FRAYTXEN1/GIOB[1]
• FRAYTXEN2/GIOB[2]

A Parameter Overlay Module (POM)

The Parameter Overlay Module (POM) is implemented as part of the L2FMC module. It is used to redirect flash memory accesses to external memory interfaces or internal SRAM. The POM has an OCP master port to redirect accesses

• Refer Section 6.9.7 : http://www.ti.com/lit/ds/symlink/tms570lc4357.pdf

AJSM

This device includes a an Advanced JTAG Security Module (AJSM) module. The AJSM provides maximum security to the memory content of the device by letting users secure the device after programming.

SCI Module (UART)

SCI abbreviation is Serial Communication Interface. usually serial communication have two categories, synchronize and asynchronous communication.

Two Different SCI Mode

• UART – Universal Asynchronous Receiver Transmitter
• USART – Universal Synchronous Asynchronous Receiver Transmitter

SCI Inettrupt

Look at the end of the file ‘sci.c’ generated by HalCoGen and see if there is an interrupt service routine there. You should see that at some point it calls ‘sciNotification’.

If your using only the “High Level” interrupt you only need to enable the channel in VIM for SCI Level 0 Interrupt (Level 0 is high priority). Same applies if you only use the low level interrupt.

SCI Hal Code Generator Configurations

1. Select Mode:  Asynchronous Mode for 1;  Synchronous Mode for 0.
2. Set Clock Mode: Internal Clock for 1; External Clock for 0.
3. Enable/Disable Interrupt for Low Level and High Level
   • RX Interrupt,
   • TX Interrupt
   • Framing Error Interrupt
   • Over Run Error Interrupt
   • Parity Error Interrupt
   • Wake Up Interrupt
   • Break Detect Interrupt
4. Baud Rate in Hz (9600, 115200)
5. Stop Bits : 1 or 2
6. Data Length : Upto 8 Bits
7. Parity Eable
8. Parity Mode : Even Parity; Odd Parity.

Reference

• http://www.ti.com.cn/cn/lit/an/spna124a/spna124a.pdf

I2C

• Support I2C Speed modes ?: Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate).
• The CPU can use seven interrupts.
• Operates with VBUS frequency from 6.7 MHz up
• Operates with module frequency between 6.7 MHz to 13.3 MHz
• Open drain control of the outputs
• I2C Module Reset Conditions: Through the global peripheral reset. A device reset causes a global peripheral reset.By clearing the IRS bit in the I2C mode register.
• START: A high-to-low transition on the SDA line while SCL is high defines the START condition.
• STOP: A low-to-high transition on the SDA line while SCL is high defines the STOP condition.

Hercules TMS570LC4357 Based Development Boards

Two Different Hercules TMS570LC4357 Dev Boards are available from TI.

• LAUNCHXL2-570LC43
• TMS570C HDK (Hercules Development Kit)

Hercules TMS570LC43x Development Kit

• Hercules development kit expends many pin out compare to TMS570C LAUNCHPADS
• Website: Product: http://www.ti.com/tool/TMDX570LC43HDK
• PDF: HDK User Guide: http://www.ti.com/lit/ug/spnu597a/spnu597a.pdf
• Reference: http://www.ti.com/tool/TMDX570LC43HDK#technicaldocuments

Pin details of HDK

GPIO	I2C	PWM	SCI / UART
GIOA[0] – A5	I2C1_SCL – C3	PWM1A – B5	UART1: SCI1TX – B7
GIOA[1] – C2	I2C1_SDA – B2	PWM1B – H3	UART1: SCI1RX – A7
GIOA[2] – B15	I2C2_SCL – G16	PWM2A – M1	UART2: SCI2TX – T5
GIOA[3] – E1	I2C2_SDA – G17	PWM2B – K18	UART2: SCI2RX – P4
GIOA[4] – A6		PWM3A – W5	UART3: SCI3TX – N2
GIOA[5] – B5 / R9		PWM3B – V6	UART3: SCI3RX – W3
GIOA[6] – H3 / R10		PWM4A – E19	UART4: SCI4TX – B13
GIOA[7] – K11		PWM4B – B12	UART4: SCI4RX – A13
GIOB[0] – M2		PWM5A – W3
GIOB[1] – K2		PWM5B – N2
GIOB[2] – B9		PWM6A – J1
GIOB[3] – R4		PWM6B – P2
GIOB[4] – G1 / L17		PWM7A – V7
GIOB[5] – G2 / M17		PWM7B – T1
GIOB[6] – J2
GIOB[7] – F1

HalCoGen

• Hardware Abstraction Layer Code Generator for Hercules MCUs it’s from Texas Instruments.
• It’s a free software available from this site : http://www.ti.com/tool/HALCOGEN
• HALCoGen allows users to generate hardware abstraction layer device drivers for Hercules™ microcontrollers.
• HALCoGen provides a graphical user interface that allows the user to configure peripherals, interrupts, clocks, and other Hercules microcontroller parameters. Once the Hercules device is configured, the user can generate peripheral initialization and driver code, which can be imported into CCS, IAR Workbench, or Keil uVision
• Application Notes: http://www.ti.com/lit/an/spna237/spna237.pdf
• Application Notes: http://www.ti.com/lit/an/spna121b/spna121b.pdf

Example Code

• lwip TCP/IP server & client example code for TMS570LC4357 and HalCoGen setting
• BootLoader
  • TMS570LC4357 Boot loader: TMS570 family is based on Cortex-R4 CPU cores which support only two alternative primary exception table start addresses. (Ref: https://lists.rtems.org/pipermail/devel/2015-November/012878.html)
  • Ethernet Boot Loader
  • UART BootLoader
  • CAN Boot Loader

Reference

• Data Sheet: http://www.ti.com/lit/pdf/spns195
• http://processors.wiki.ti.com/index.php/HALCoGen_Ethernet_Driver_and_lwIP_Integration_Demonstration
• https://training.ti.com/hercules-how-tutorial-ethernet
• Refer : Page number 207, data sheet : “spns195c.pdf“
• Refer : Page number 1803, data sheet : “spnu563.pdf“
• TMS570LC43-HDK Ethernet Interface details : http://www.ti.com/lit/ug/spnu597a/spnu597a.pdf/
• https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/493611?lwip-TCP-IP-server-client-example-code-for-TMS570LC4357-and-HalCoGen-setting-#pi320995=1
• http://processors.wiki.ti.com/index.php/LAUNCHXL2_570LC43:_lwIP_Demo
• https://e2e.ti.com/support/archive/launchyourdesign/m/boosterpackcontest/666164
• Ethernet Loop Back : http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/683305?TMS570LC4357-Ethernet-not-getting-initialized
• Ethernet HALCoGen Sttings: https://e2e.ti.com/support/archive/launchyourdesign/m/boosterpackcontest/666058
• https://www.hackster.io/jancumps/hercules-configure-memory-cache-for-dma-0945cd
• TI Assemply Guide: https://www.ti.com/lit/ug/spnu118y/spnu118y.pdf
• Memory : https://sourceware.org/binutils/docs/ld/MEMORY.html
• Section: https://sourceware.org/binutils/docs/ld/SECTIONS.html
• https://downloads.ti.com/docs/esd/SPRU514/sections-stdz0542969.html
• Technical Reference Manual : spnu563a :  http://www.ti.com/lit/ug/spnu563a/spnu563a.pdf
• http://www.bdtic.com/en/ti/tms570lc4357
• http://www.ti.com/lit/er/spnz180d/spnz180d.pdf
• https://www.digchip.com/datasheets/8755934-tms570lc4357-16-and-32-bit.html