I²C (Inter Integrated Circuit) is a bi-directional two wires and serial data transmission communication protocol developed by Philips (Now NXP Semiconductor) at 1982. I2C is a Half-duplex communication protocol – (I2c can’t send and receive same time in bus-Data line). Multi master can communicate with multi salve. (Note : Can’t Communicate one master to another master, One master can communicate with single slave or multi slave). I2C is a Level Triggering. A device that sends data onto the bus is defined as transmitter, and a device receiving data is defined as receiver. The bus has to be controlled by a master device which generates the Start and Stop conditions, while the Some devices like LCD, EEPROM, RTC are works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
Image Link
Contents
- 1 I2C Applications & Uses
- 2 I2C Feature
- 3 I2C Revisions
- 4 I2C Operating Speed Mode
- 5 I2C Addressing methods
- 6 I²C Address Allocation Table
- 7 I2C Basic Design
- 8 I2C Message protocols
- 9 I2C Master & Salve function
- 10 I2C Physical Layer
- 11 I2C Pull-up resistor
- 12 I2C Data Frame
- 12.1 I2C Bus Characteristics
- 12.2 I2C Bus Busy :
- 12.3 I2C Bus Free :
- 12.4 I2C Start (S) Condition
- 12.5 I2C Stop (P) Condition
- 12.6 I2C Repeated Start (Sr) Condition
- 12.7 I2C Data Valid condition
- 12.8 I2C data transfer condition
- 12.9 I2C read/write conditions
- 12.10 I2c Acknowledgement (ACK) Condition
- 12.11 I2C Not Acknowledgement (NACK) Condition
- 13 I2C Clock Synchronization
- 14 I2C Clock Stretching
- 15 I2C Arbitration
- 16 I2C Single master with multi-slave connection diagram
- 17 i2C Multi-Master with Multi-Slave connection diagram
- 18 I2C LM75 Temperature Data format Example
- 19 I2C Advantages & Disadvantage
- 20 I2C Tools and Analyzer
- 21 I2C Protocol Interview Questions
- 22 I2C Interface Example
- 23 Refer Websites
I2C Applications & Uses
- I2C Applications : System Management Bus (SMBus), Power Management Bus (PMBus), Intelligent Platform , Management Interface (IPMI), Display Data Channel (DDC), Advanced Telecom Computing Architecture (ATCA)
- I2C Uses : I2C can be used to control a wide range of devices: analogue-to-digital and digital-to-analog converters (ADCs and DACs), LCD and OLED displays, keyboards, LED and motor drivers, memory chips and cards (EEPROM, RAM, FERAM, Flash), pressure and temperature sensors and other peripheral devices.
- I2C GPIO Extender – Microchip’s MCP23008(8channel), Microchip’s MCP23017(16channel), Texas Instruments pcf8574(8chennel).
- I2C RTC (DS1337).
I2C Feature
- 1000 different IC’s manufactured are available 50 more companies.
- There’s an allowance for multiple clock-masters on the same bus
I2C Revisions
Year -Version | Describtion |
1982 | 100 KHz I²C Simple Internal Bus (Philips Chips) |
1992 – Version 1 | 400 KHz fast Mode (Fm) 10 Bit addressing mode 1008Nodes First Standardized Version 400 Kbit/s |
1998-Version 2 | 3.4 MHz High Speed mode (Hs) Power saving requirement for electric voltage and current 3.4 Mbit/s |
2000 – Version 2.1 | Minor clean-up of version 2 |
2007 – Version 3 | 1 MHz Fast mode plus (Fm+) Device ID Mechanisms 1 Mbit/s |
2012 – Version 4 | 5 MHz Ultra-fast mode (UFm) New USDA and USCL lines using push pull logic without pull-up resistors Added assigned manufacturer ID table |
2012 – Version 5 | Corrected mistakes |
2014 – Version 6 | Corrected graph, This is most recent standard |
I2C Operating Speed Mode
Type | Mode | Speed | Applications |
Bidirectional Bus | Low speed mode | 10 Kbit/s | |
Standard mode (Sm) | 100 Kbit/s | ||
Fast mode (Fm) | 400 Kbit/s | Embedded Systems & PCs usual Speed | |
Fast mode plus (Fm+) | 1 Mbit/s | ||
High Speed mode (Hs-mode) | 3.4 Mbit/s | ||
Unidirectional Bus | Ultra-Fast mode (UFm) | 5 Mbit/s |
I2C Addressing methods
I2C Addressing 7Bit
- 7bit addressing mode have 128 address line and maximum 112 Slave node can be connect masters.
I2C Addressing 10bit
- 10 Bit addressing mode have 1024 address line and maximum 1008 slave Nodes can be connect masters
- Two address words are used for device addressing instead of one.
- The first address word MSBs are conventionally coded as “11110” so any device on the bus is aware the master sends a 10 bits device address
I²C Address Allocation Table
The group number represents the hexadecimal equivalent of the four most significant bits of the slave address (A6-A3).
- Download : I²C-address-allocation-table.pdf
- Note : X = Don’t care, A = Programmable address bit, P = Page selection bit
GROUP(1) | TYPE NUMBER | DESCRIPTION | ||
Group 0 (0000 | ||||
0 | 0 | 0 | – | General call address |
X | X | X | – | Reserved addresses |
Group 1 (0001) | ||||
1 | A1 | A0 | SAA2530 | ADR/DMX digital receiver |
1 | A1 | A0 | TDA8045 | QAM-64 demodulator |
Group 2 (0010) | ||||
0 | 0 | A0 | SAA4700/T | VPS dataline processor |
0 | 0 | A0 | SAA5233 | Dual standard PDC decoder |
0 | 0 | 1 | SAA5243 | Computer controlled teletext circuit |
0 | 0 | 1 | SAA5244 | Integrated VIP and teletext |
0 | 0 | 1 | SAA5245 | 525-line teletext decoder/controller |
0 | 0 | 1 | SAA5246A | Integrated VIP and teletext |
0 | 0 | 1 | SAA5249 | VIP and teletext controller |
0 | A1 | A0 | CCR921 | RDS/RBDS decoder |
0 | A1 | A0 | SAF1135 | Dataline 16 decoder for VPS (call array) |
1 | 0 | 0 | SAA5252 | Line 21 decoder |
1 | 1 | A0 | SAB9075H | PIP controller for NTSC |
Group 3 (0011) | ||||
0 | 0 | A0 | SAA7370 | CD-decoder plus digital servo processor |
0 | A1 | A0 | PCD5096 | Universal codec |
0 | 1 | A0 | SAA2510 | Video-CD MPEG-audio/video decoder |
0 | 1 | 1 | PDIUSB11 | Universal serial bus |
1 | 0 | 1 | SAA2502 | MPEG audio source decoder |
1 | 1 | A0 | SAA1770 | D2MAC decoder for satellite and cable TV |
Group 4 (0100) | ||||
0 | 0 | 0 | SAA6750 | MPEG2 encoder for Desk Top Video (=SAA7137) |
0 | 0 | 0 | TDA9177 | YUV transient improvement processor |
0 | 0 | 0 | TDA9178 | YUV transient improvement processor |
0 | 0 | A0 | PCA1070 | Programmable speech transmission IC |
0 | A1 | A0 | PCF8575 | Remote 16-bit I/O expander |
0 | A1 | A0 | PCF8575C | Remote 16-bit I/O expander |
0 | A1 | A0 | SAA1300 | Tuner switch circuit |
A2 | A1 | A0 | TDA8444 | Octuple 6-bit DAC |
A2 | A1 | A0 | PCF8574 | 8-bit remote I/O port (I2C-bus to parallel converter) |
1 | 0 | A0 | PCD3311C | DTMF/modem/musical tone generator |
1 | 0 | A0 | PCD3312C | DTMF/modem/musical tone generator |
1 | 1 | 1 | PCD5002 | Pager decoder |
Group 6 (0110) | ||||
0 | 0 | 0 | SAA5301 | MOJI processor for Japan/China |
0 | 1 | 1 | PCE84C467/8 | 8-bit CMOS auto-sync monitor controller |
0 | 1 | 1 | PCE84C882 | 8-bit microcontroller for monitor applications |
0 | 1 | 1 | PCE84C886 | 8-bit microcontroller for monitor applications |
Group 7 (0111) | ||||
0 | 0 | A0 | SAA7140B | High performance video scaler |
0 | 0 | A0 | PCF8533 | Universal LCD driver for low multiplex rates |
0 | 0 | A0 | PCF8576 | 16-segment LCD driver 1:1 – 1:4 Mux rates |
0 | 0 | A0 | PCF8576C | 16-segment LCD driver 1:1 – 1:4 Mux rates |
0 | A1 | A0 | SAA1064 | 4-digit LED driver |
A2 | A1 | A0 | PCF8574A | 8-bit remote I/O port (I2C-bus to parallel converter) |
0 | 1 | 0 | PCF8577C | 32/64-segment LCD display driver |
0 | 1 | A0 | PCF2103 | LCD controller/driver |
0 | 1 | A0 | PCF2104 | LCD controller/driver |
0 | 1 | A0 | PCF2105 | LCD controller/driver |
0 | 1 | A0 | PCF2113 | LCD controller/driver |
0 | 1 | A0 | PCF2119 | LCD controller/driver |
0 | 1 | A0 | SAA2116 | LCD controller/driver |
1 | 0 | A0 | PCF8531 | 34 X 128 pixel matrix driver |
1 | 0 | A0 | PCF8548 | 65 X 102 pixels matrix LCD driver |
1 | 0 | A0 | PCF8549 | 65 X 102 pixels matrix LCD driver |
1 | 0 | A0 | PCF8578/9 | Row/column LCD dot matrix driver/display |
1 | 0 | A0 | PCF8568 | LCD row driver for dot matrix displays |
1 | 0 | A0 | PCF8569 | LCD column driver for dot matrix displays |
1 | A1 | A0 | PCF8535 | 65 X 133 pixel matrix LCD driver |
1 | 1 | A0 | OM4085 | Universal LCD driver for low multiplex rates |
1 | 1 | A0 | PCF8566 | 96-segment LCD driver 1:1 – 1:4 Mux rates |
Group 8 (1000) | ||||
0 | 0 | 0 | TEA6300 | Sound fader control and preamplifier/source selector |
0 | 0 | 0 | TEA6320/1/2/3 | Sound fader control circuit |
0 | 0 | 0 | TEA6330 | Tone/volume controller |
0 | 0 | A0 | NE5751 | Audio processor for RF communication |
0 | 0 | A0 | TDA8421 | Audio processor |
0 | 0 | A0 | TDA9860 | Hi-fi audio processor |
0 | 0 | 1 | TDA8424/5/6 | Audio processor |
0 | 1 | 0 | TDA8415 | TV/VCR stereo/dual sound processor |
0 | 1 | 0 | TDA8417 | TV/VCR stereo/dual sound processor |
0 | 1 | 0 | TDA9840 | TV stereo/dual sound processor |
0 | 1 | A0 | TDA8480T | RGB gamma-correction processor |
1 | 0 | 0 | TDA4670/1/2 | Picture signal improvement (PSI) circuit |
1 | 0 | 0 | TDA4680/5/7/8 | Video processor |
1 | 0 | 0 | TDA4780 | Video control with gamma control |
1 | 0 | 0 | TDA4885 | 150 MHz video controller |
1 | 0 | 0 | TDA8442 | Interface for colour decoder |
1 | 0 | 1 | TDA8366 | Multistandard one-chip video processor |
1 | 0 | 1 | TDA8373 | NTSC one-chip video processor |
1 | 0 | 1 | TDA8374 | Multistandard one-chip video processor |
1 | 0 | 1 | TDA8375/A | Multistandard one-chip video processor |
1 | 0 | 1 | TDA8376/A | Multistandard one-chip video processor |
1 | 0 | 1 | TDA9161A | Bus-controlled decoder/sync. processor |
1 | A1 | 1 | SAA7151B | 8-bit digital multistandard TV decoder |
1 | A1 | 1 | SAA7191B | Digital multistandard TV decoder |
1 | A1 | 1 | SAA9056 | Digital SCAM colour decoder |
1 | A1 | 1 | TDA9141/3/4 | Alignment-free multistandard decoder |
1 | A1 | 1 | TDA9160 | Multistandard decoder/sync. processor |
1 | A1 | 1 | TDA9162 | Multistandard decoder/sync. processor |
1 | 1 | 0 | TDA4853/4 | Autosync deflection processor |
1 | 1 | 0 | TDA9150B | Deflection processor |
1 | 1 | 0 | TDA9151B | Programmable deflection processor |
1 | 1 | A0 | TEA6360 | 5-band equalizer |
1 | 1 | A0 | TDA8433 | TV deflection processor |
Group 9 (1001) | ||||
A2 | A1 | A0 | PCF8591 | 4-channel, 8-bit Mux ADC and one DAC |
A2 | A1 | A0 | TDA8440 | Video/audio switch |
A2 | A1 | A0 | TDA8540 | 4 X 4 video switch matrix |
1 | A1 | A0 | TDA8752 | Triple fast ADC for LCD |
1 | 1 | A0 | SAA7110A | Digital multistandard decoder |
Group A (1010) | ||||
0 | 0 | A0 | SAA7199B | Digital multistandard encoder |
0 | 1 | 0 | TDA8416 | TV/VCR stereo/dual sound processor |
0 | 1 | A0 | TDA9850 | BTSC stereo/SAP decoder |
0 | 1 | A0 | TDA9855 | BTSC stereo/SAP decoder |
0 | 1 | 1 | TDA9852 | BTSC stereo/SAP decoder |
1 | 0 | 0 | TDA9610 | Audio FM processor for VHS |
1 | 0 | 0 | TDA9614H | Audio processor for VHS |
1 | A1 | 0 | SAA7186 | Digital video scaler |
1 | 0 | 1 | PCA8516 | Stand-alone OSD IC |
1 | 1 | 1 | SAA7165 | Video enhancement D/A processor |
1 | 1 | 1 | SAA9065 | Video enhancement and D/A processor |
Group B (1011) | ||||
0 | 0 | A0 | SAA7199B | Digital multistandard encoder |
0 | 1 | 0 | TDA8416 | TV/VCR stereo/dual sound processor |
0 | 1 | A0 | TDA9850 | BTSC stereo/SAP decoder |
0 | 1 | A0 | TDA9855 | BTSC stereo/SAP decoder |
0 | 1 | 1 | TDA9852 | BTSC stereo/SAP decoder |
1 | 0 | 0 | TDA9610 | Audio FM processor for VHS |
1 | 0 | 0 | TDA9614H | Audio processor for VHS |
1 | A1 | 0 | SAA7186 | Digital video scaler |
1 | 0 | 1 | PCA8516 | Stand-alone OSD IC |
1 | 1 | 1 | SAA7165 | Video enhancement D/A processor |
1 | 1 | 1 | SAA9065 | Video enhancement and D/A processor |
Group C (1100) | ||||
0 | 0 | 1 | TEA6100 | FM/IF for computer-controlled radio |
0 | 1 | 0 | TEA6821/2 | Car radio AM |
0 | 1 | 0 | TEA6824T | Car radio IF IC |
0 | A1 | A0 | TSA5511/2/4 | 1.3 GHz PLL frequency synthesizer for TV |
0 | A1 | A0 | TSA5522/3M | 1.4 GHz PLL frequency synthesizer for TV |
0 | 1 | A0 | TDA8735 | 150 MHz PLL frequency synthesizer |
0 | 1 | A0 | TSA6057 | Radio tuning PLL frequency synthesizer |
0 | 1 | A0 | TSA6060 | Radio tuning PLL frequency synthesizer |
0 | 1 | A0 | UMA1014 | Frequency synthesizer for mobile telephones |
1 | 0 | 0 | TDA8722 | Negative video modulator with FM sound |
Group D (1101) | ||||
0 | 0 | A0 | TDA8043 | QPSK demodulator and decoder |
0 | 0 | A0 | TDA9170 | YUV processor with picture improvement |
0 | A1 | A0 | PCF8573 | Clock/calendar |
A2 | A1 | A0 | TDA8443A | YUV/RGB matrix switch |
0 | 1 | A0 | TDA8745 | Satellite sound decoder |
1 | 0 | 0 | TDA1551Q | 2 ´ 22 W BTL audio power amplifier |
1 | A1 | A0 | TDA4845 | Vector processor for TV-pictures tubes |
1 | A1 | A0 | UMA1000T | Data processor for mobile telephones |
1 | 1 | A0 | PCD4440 | Voice scrambler/descrambler for mobile telephones |
Group E (1110) | ||||
0 | 0 | 0 | PCD3316 | Caller-ID on Call Waiting (CIDCW) receiver |
0 | 0 | 0 | TDA9177 | 2nd address for LTI (1st is ’40’) |
0 | 0 | 0 | TDA9178 | 2nd address for LTI (1st is ’40’) |
0 | 0 | A0 | SAA7192 | Digital colour space-converter |
Group F (1111) | ||||
X | X | X | – | Reserved addresses |
Group 0 to F (0000 to 1111) | ||||
X | X | X | PCF8584 | I2C-bus controller |
I2C Basic Design
SDA (Serial Data Line)
- Master device (Master node)
- Node that generates the clock and initiates communication with slave
- Slave device (Slave node)
- Node that receives the clock and responds when addressed by master
- The maximum number of nodes is limited by the address space, and by the total bus capacitance of 400 pF.
- Note : Basically SDA and SCL Open drain (So need Pulled up resistor)
I2C Message protocols
I²C defines basic types of messages, each of which begins with a START and ends with a STOP:
- Single message where a master writes data to a slave;
- Single message where a master reads data from a slave;
- Combined messages, where a master issues at least two reads and/or writes to one or more slaves.
I2C Master & Salve function
Device | Function Role |
Master device |
|
Slave device |
|
Transmitter/Receiver |
|
I2C Physical Layer
- Device count limit : max capacitance 400pF
I2C Pull-up resistor
Centrally suggest used Pull-up resistor for i2c communication scl and sda line is 2Kohm for 100Kbps and 10Kohm for 400Kbps. Refer this : http://www.ti.com/lit/an/slva689/slva689.pdf
I2C Minimum pull-up resistor value
- The minimum resistance is pretty easy to determine, and is based on the bus voltage (Vbus), the maximum voltage that can be read as a logic-low (VOL), and the maximum current that the pins can sink when at or below VOL (IOL).
- Formula : Rp(min) = (Vbus – VOL) / IOL
I2C Minimum pull-up resistor value
- The maximum pull-up resistance is based on the needed rise-time of the clock (dependent on the I2C clock frequency), and the total capacitance on the bus. The I2C specification (http://cache.nxp.com/documents/user_manual/UM10204.pdf) lists the maximum total bus capacitance with a pull-up resistor to be 200 pF (it can be up to 400 pF if the pull-up is a current source, section 5.1). This specification also describes the rise-time of SDA/SCL to be a maximum of 300 ns in “Fast-mode” – 400 kHz.
- Formula : Rp(min) = rt / ( 0.8473 * Cb )
- Where rt is the maximum allowed rise-time of the bus, and Cb is the total bus capacitance.
I2C Pull-up resistor Example
- Rp(Max) = tr/(0.8473*Cb) = (3000*10^-9)/(0.8473* (200*10^-12)) = 1.77kohm
- Rp(Min) = (Vcc-Vol)/Iol = (3.3-0.4)/3*10^-3) = 966.667ohm
I2C Data Frame
Transmission is byte oriented
I2C Bus Characteristics
- Data transfer may be initiated only when the bus is not busy(Free).
-
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition.
- An Acknowledge bit must follow each byte.
I2C Bus Busy :
- After Start(S) and before(P) state
I2C Bus Free :
- Before Start(S) and after Stop(P)
- Both data and clock lines remain high
I2C Start (S) Condition
- A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.
I2C Stop (P) Condition
- low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition.
I2C Repeated Start (Sr) Condition
I2C Data Valid condition
- Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device.
I2C data transfer condition
- Data is transferred with the Most Significant Bit (MSB) first. An Acknowledge bit must follow each byte.
I2C read/write conditions
- The last bit of the control byte defines the operation to be performed. When set to a ‘1’ a read operation is selected, and when set to a ‘0’ a write operation is selected.
I2c Acknowledgement (ACK) Condition
- A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse.
- The master generates all clock pulses, including the acknowledge clock pulse.
I2C Not Acknowledgement (NACK) Condition
I2C Clock Synchronization
I2C Clock Stretching
If a slave is pulling the clock down, it’s called “clock-stretching” and is a signal to the master to pause until the slave is ready.
The Below diagram is raspberry bi i2c clock stretching
I2C Arbitration
- What will happens if the two masters are write different data to same slave-1 in I2C?
- What will happens if the two masters are write same data to same slave-1 in I2c?
- How to know the data of master-1 or master-2 writes same data in slave-1?(conditions : if two masters are write same data to same slave-1, in I2c)
- What will happens if the two masters are read data from same slave-1 in I2c?
I2C Single master with multi-slave connection diagram
i2C Multi-Master with Multi-Slave connection diagram
I2C LM75 Temperature Data format Example
Example 1 : LM75 temperature sensor in its easiest mode, the master sends the address and a read bit, and then reads two bytes back. Since the master sent the address, the slave acknowledges to say it’s ready. Then the slave sends a byte, which the master acknowledges with an ACK
. Then the slave sends the second byte, to which the master responds with a NACK
and a stop signal to say it’s done.
1 2 3 4 5 6 7 8 |
Master: Start Signal Master: Address + Read Bit Slave: ACK Slave: First byte of data Master: ACK Slave: Second / last byte of data Master: NACK Master: Stop Signal |
Example 2 : Wrapping up the protocol, there’s also multi-part communications. If the master needs to send a byte to the slave, and then read some bytes back, for example, it needs to first send the address with a write signal and then re-send the address with the read signal. To signal the change of mode, the master sends the so-called “repeated start” signal, which is just a regular start signal when there’s been no preceding stop. Again, here’s an example with the LM75, first telling the LM75 that is wishes to read the high temperature setting, and then reading the two bytes back.
1 2 3 4 5 6 7 8 9 10 11 12 13 |
Master: Start Signal Master: Address + Write Bit Slave: ACK Master: Set the high-temperature register for reading Slave: ACK Master: (Re-) Start Signal Master: Address + Read Bit Slave: ACK Slave: First byte of data Master: ACK Slave: Second / last byte of data Master: NACK Master: Stop Signal |
I2C Advantages & Disadvantage
I2C Advantage
- Only uses two wires
- Supports multiple masters and multiple slaves
- ACK/NACK bit gives confirmation that each frame is transferred successfully
- Hardware is less complicated than with UARTs
- Well known and widely used protocol
I2C Disadvantages
- Slower data transfer rate than SPI
- The size of the data frame is limited to 8 bits
- More complicated hardware needed to implement than SPI
I2C Tools and Analyzer
I2C Protocol Interview Questions
Q : What is I2C ?
- I2C is Inter Interconnected Circuited
Q : Who developed the i2c communication protocol?
- I2C is developed by Philips (Now NXP Semiconductor).
Q : When the I2C communication protocol was developed?
- I2C is developed by Philips (Now NXP Semiconductor) at 1982.
Q : I2C is half duplex or full duplex?
- I2C is Half Duplex. Because this I2C communication can’t able to master send data to slave or slave send data to master in same time.
Q : I2C is Synchronous or Asynchronous Communication?
- Synchronous Communication, Because Master generate the clock signal and slave synchronous with the master clock signal. so this i2c communication is synchronous communication
Q: I2C is a Serial or Parallel communication?
- I2C is serial communication. required one data line for transmit all byte of data to the destination.
Q : I2C is Edge Triggering or Level Triggering?
- I2C is Level Triggering.
Q : How many line required for I2C communication bus?
- Two lines required for I2C Communication. That are SCL and SDA.
Q : What is mean by SDA line in I2C communication bus?
- SDA – Serial DAta line
Q : What is mean by SCL line in I2C communication bus?
- SCL – Serial CLock Line
Q : Why required Pull up resistor connection for I2C?
- System Bus lines are SCL and SDA are designed by Open drain logic, So required pullup resistor for making SDA & SCL line as high/low.
Q : Why you require two pull up resistor for SCL & SDA? : Answer will add soon.
Q : Why not require one pull up resistor for i2c even SCL or SDA? : Answer will add soon.
Q : How you select I2C Pull up resistor?
Based on the i2c bus operating speed can be select the pull up resistor
- Its Depends up on the Bus capacitance.
- 2Kohm for 100Kbps
- 10Kohm for 400Kbps
Q : What are the i2c communication speed modes ?
- Slow mode, Standard mode, Fast mode, Fast plus mode, Ultra fast mode.
Q : How to set i2c speed in Master device?
Some device have default speed rate. most of the embedded micro-controllers support the standard mode(sm) 100kbs, fast mode(fm) 400kbs, fast mode plus (fm+) 1.2kbs, High speed mode(hs-mode) 3.4kbs.
- ESP8266
- Arduino I2C you can use function to set Wire.setClock(Speed_value) , I2C slave devices have no minimum working clock frequency, however 100KHz is usually the baseline. clockFrequency: the value (in Hertz) of desired communication clock. Accepted values are 100000 (standard mode) and 400000 (fast mode). Some processors also support 10000 (low speed mode), 1000000 (fast mode plus) and 3400000 (high speed mode). Please refer to the specific processor documentation to make sure the desired mode is supported. for more See this
- For more see this
Q : How to set i2c speed in Slave device?
- We can’t able to set slave speed. because i2c master generates the clock signal. Slave device only sync with master clock
- Single slave supports various operating speeds
- Microchip MCP23008 supports 100kHz, 400kHz, 1.7MHz.
- Microchip MCP23017 supports 100kHz, 400kHz, 1.7MHz.
Q : What are the different addressing modes are available for i2c communication
- Two different addressing modes are available for i2c communication.
- 7-bit addressing
- 8-bit addressing
Q : How to set the address of the slave in I2C communication?
- By selecting the hardware address lines in slave. make high or low in the hardware level, its depends up on the salve manufactures
Q : I2C Master can communicate in same bus with one 7bit address slave and another 10bit address slave ?
Q : Whats is Slew Rate in I2C?
Q : What is transition time in I2C?
Q : What is address collision in I2C?
Q : Draw the I2C basic Connection Diagram? : Will Add Soon.
Q : Draw the i2c data frame for 7 bit addressing mode?
Q : Draw the i2c data frame for 10 bit addressing mode?
Q : Draw the i2c start bit condition signal?
Q : Draw the i2c stop bit communication signal?
Q : Draw the i2c repeat start bit communication signal?
Q : Draw the i2c acknowledgement bit communication signal?
Q : Draw the i2c non-acknowledgement bit communication signal?
Q : What is I2C clock Stretching?
Q : What is I2C clock synchronization?
Q : Draw the I2C clock synchronization signal?Q : What is I2C Arbitration?
Q : Maximum length of the I2C Cable can use?
- I was working up-to 3 meters RJ45 cable(LAN cable).
Q : What are the limitations of I2C interface?
I2C Interview questions Reference Links
I2C Interface Example
- ESP8266 NodeMCU Module I2C : https://aruneworld.com/embedded/esp8266/esp8266-nodemcu/esp8266-nodemcu-module-i2c/
- ESP32 NodeMCU Module I2C : https://aruneworld.com/embedded/esp32/esp32-nodemcu/esp32-nodemcu-module-i2c/
- PIC Micro-Controller interface with I2C : https://electrosome.com/i2c-pic-microcontroller-mplab-xc8/
Refer Websites
- Wikipedia_I²C
- Everything about I²C
- Official I²C specification (free), NXP
- List of assigned NXP / Philips I²C addresses (free), NXP
- 7-bit, 8-bit, and 10-bit I²C Slave Addressing
- PDF – I²C-bus specification n and user manual By NXP
- https://www.I²C-bus.org
- https://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/
- https://en.m.wikipedia.org/wiki/Bit_banging
- http://codinglab.blogspot.com/2008/10/i2c-on-avr-using-bit-banging.html
- http://dlnware.com/dll/I2C-Bus-Interface-CC-API
- https://hackaday.com/2016/07/19/what-could-go-wrong-i2c-edition/
- How communicate two I²C masters? : https://www.I²C-bus.org/multimaster/
- I2C YouTube Videos :
- https://youtu.be/RPHP4fAisz8
- I2c Protocol Analyzer Tool Video : https://www.youtube.com/watch?v=Ggvw8K12FuE