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Embedded Protocol – I2C

 I²C (Inter-Integrated Circuit) is a bi-directional two wires and serial data transmission communication protocol developed by  Philips (Now NXP Semiconductor) in 1982. I2C is a Half-duplex communication protocol  – (I2c can’t send and receive same time in the bus-data line). Multi-master can communicate with multi-salve. (Note: Communication is restricted between two masters; however, a single master can communicate with either a single slave or multiple slaves.) I2C is a Level Triggering. A device that sends data onto the bus is defined as a transmitter, and a device receiving data is defined as a receiver.

The bus must be controlled by a master device, responsible for generating the Start and Stop conditions. In contrast, certain devices such as LCDs, EEPROMs, and RTCs function as slaves. It’s important to note that both master and slave devices can operate as either transmitters or receivers. However, the master device plays a pivotal role in determining which mode is activated.

Applications & Uses

  • I2C Applications : System Management Bus (SMBus), Power Management Bus (PMBus), Intelligent Platform , Management Interface (IPMI), Display Data Channel (DDC), Advanced Telecom Computing Architecture (ATCA)
  • I2C Uses : I2C can be used to control a wide range of devices: analogue-to-digital and digital-to-analog converters (ADCs and DACs), LCD and OLED displays, keyboards, LED and motor drivers, memory chips and cards (EEPROM, RAM, FERAM, Flash), pressure and temperature sensors and other peripheral devices.
    • I2C GPIO Extender – Microchip’s MCP23008(8channel),  Microchip’s MCP23017(16channel), Texas Instruments pcf8574(8chennel).
    • I2C RTC (DS1337).

Feature

  • 1000 different IC’s manufactured are available 50 more companies.
  • There’s an allowance for multiple clock-masters on the same bus

Revisions


Operating Speed Mode


Addressing methods

I2C Addressing 7Bit

  • In the 7-bit addressing mode, comprising 128 address lines, the system allows a maximum of 112 slave nodes to be connected to the masters.

I2C Addressing 10bit

  • In the 10-bit addressing mode, which provides a vast address space with 1024 address lines, a maximum of 1008 slave nodes can be connected to the masters.
  • Two address words are used for device addressing instead of one.
  • The first address word MSBs are conventionally coded as “11110” so any device on the bus is aware the master sends a 10 bits device address

I²C Address Allocation Table

The group number represents the hexadecimal equivalent of the four most significant bits of the slave address (A6-A3).

  • Note : X = Don’t care, A = Programmable address bit, P = Page selection bit

Address Allocation Table Group 01 to 05

GROUP(1)TYPE NUMBERDESCRIPTION
Group 0 (0000
000General call address
XXXReserved addresses
Group 1 (0001)
1A1A0SAA2530ADR/DMX digital receiver
1A1A0TDA8045QAM-64 demodulator
Group 2 (0010)
00A0SAA4700/TVPS dataline processor
00A0SAA5233Dual standard PDC decoder
001SAA5243Computer controlled teletext circuit
001SAA5244Integrated VIP and teletext
001SAA5245525-line teletext decoder/controller
001SAA5246AIntegrated VIP and teletext
001SAA5249VIP and teletext controller
0A1A0CCR921RDS/RBDS decoder
0A1A0SAF1135Dataline 16 decoder for VPS (call array)
100SAA5252Line 21 decoder
11A0SAB9075HPIP controller for NTSC
Group 3 (0011)
00A0SAA7370CD-decoder plus digital servo processor
0A1A0PCD5096Universal codec
01A0SAA2510Video-CD MPEG-audio/video decoder
011PDIUSB11Universal serial bus
101SAA2502MPEG audio source decoder
11A0SAA1770D2MAC decoder for satellite and cable TV
Group 4 (0100)
000SAA6750MPEG2 encoder for Desk Top Video (=SAA7137)
000TDA9177YUV transient improvement processor
000TDA9178YUV transient improvement processor
00A0PCA1070Programmable speech transmission IC
0A1A0PCF8575Remote 16-bit I/O expander
0A1A0PCF8575CRemote 16-bit I/O expander
0A1A0SAA1300Tuner switch circuit
A2A1A0TDA8444Octuple 6-bit DAC
A2A1A0PCF85748-bit remote I/O port (I2C-bus to parallel converter)
10A0PCD3311CDTMF/modem/musical tone generator
10A0PCD3312CDTMF/modem/musical tone generator
111PCD5002Pager decoder

Address Allocation Table Group 06 & 07 (Cont..)

GROUP(1)TYPE NUMBERDESCRIPTION
Group 6 (0110)
000SAA5301MOJI processor for Japan/China
011PCE84C467/88-bit CMOS auto-sync monitor controller
011PCE84C8828-bit microcontroller for monitor applications
011PCE84C8868-bit microcontroller for monitor applications
Group 7 (0111)
00A0SAA7140BHigh performance video scaler
00A0PCF8533Universal LCD driver for low multiplex rates
00A0PCF857616-segment LCD driver 1:1 – 1:4 Mux rates
00A0PCF8576C16-segment LCD driver 1:1 – 1:4 Mux rates
0A1A0SAA10644-digit LED driver
A2A1A0PCF8574A8-bit remote I/O port (I2C-bus to parallel converter)
010PCF8577C32/64-segment LCD display driver
01A0PCF2103LCD controller/driver
01A0PCF2104LCD controller/driver
01A0PCF2105LCD controller/driver
01A0PCF2113LCD controller/driver
01A0PCF2119LCD controller/driver
01A0SAA2116LCD controller/driver
10A0PCF853134 X 128 pixel matrix driver
10A0PCF854865 X 102 pixels matrix LCD driver
10A0PCF854965 X 102 pixels matrix LCD driver
10A0PCF8578/9Row/column LCD dot matrix driver/display
10A0PCF8568LCD row driver for dot matrix displays
10A0PCF8569LCD column driver for dot matrix displays
1A1A0PCF853565 X 133 pixel matrix LCD driver
11A0OM4085Universal LCD driver for low multiplex rates
11A0PCF856696-segment LCD driver 1:1 – 1:4 Mux rates

Address Allocation Table Group 08 (Cont..)

GROUP(1)TYPE NUMBERDESCRIPTION
Group 8 (1000)
000TEA6300Sound fader control and preamplifier/source selector
000TEA6320/1/2/3Sound fader control circuit
000TEA6330Tone/volume controller
00A0NE5751Audio processor for RF communication
00A0TDA8421Audio processor
00A0TDA9860Hi-fi audio processor
001TDA8424/5/6Audio processor
010TDA8415TV/VCR stereo/dual sound processor
010TDA8417TV/VCR stereo/dual sound processor
010TDA9840TV stereo/dual sound processor
01A0TDA8480TRGB gamma-correction processor
100TDA4670/1/2Picture signal improvement (PSI) circuit
100TDA4680/5/7/8Video processor
100TDA4780Video control with gamma control
100TDA4885150 MHz video controller
100TDA8442Interface for colour decoder
101TDA8366Multistandard one-chip video processor
101TDA8373NTSC one-chip video processor
101TDA8374Multistandard one-chip video processor
101TDA8375/AMultistandard one-chip video processor
101TDA8376/AMultistandard one-chip video processor
101TDA9161ABus-controlled decoder/sync. processor
1A11SAA7151B8-bit digital multistandard TV decoder
1A11SAA7191BDigital multistandard TV decoder
1A11SAA9056Digital SCAM colour decoder
1A11TDA9141/3/4Alignment-free multistandard decoder
1A11TDA9160Multistandard decoder/sync. processor
1A11TDA9162Multistandard decoder/sync. processor
110TDA4853/4Autosync deflection processor
110TDA9150BDeflection processor
110TDA9151BProgrammable deflection processor
11A0TEA63605-band equalizer
11A0TDA8433TV deflection processor

Address Allocation Table Group 09 (Cont..)

GROUP(1)TYPE NUMBERDESCRIPTION
Group 9 (1001)
A2A1A0PCF85914-channel, 8-bit Mux ADC and one DAC
A2A1A0TDA8440Video/audio switch
A2A1A0TDA85404 X 4 video switch matrix
1A1A0TDA8752Triple fast ADC for LCD
11A0SAA7110ADigital multistandard decoder


Address Allocation Table Group A to C (Cont..)

GROUP(1)TYPE NUMBERDESCRIPTION
Group A (1010)
00A0SAA7199BDigital multistandard encoder
010TDA8416TV/VCR stereo/dual sound processor
01A0TDA9850BTSC stereo/SAP decoder
01A0TDA9855BTSC stereo/SAP decoder
011TDA9852BTSC stereo/SAP decoder
100TDA9610Audio FM processor for VHS
100TDA9614HAudio processor for VHS
1A10SAA7186Digital video scaler
101PCA8516Stand-alone OSD IC
111SAA7165Video enhancement D/A processor
111SAA9065Video enhancement and D/A processor
Group B (1011)
00A0SAA7199BDigital multistandard encoder
010TDA8416TV/VCR stereo/dual sound processor
01A0TDA9850BTSC stereo/SAP decoder
01A0TDA9855BTSC stereo/SAP decoder
011TDA9852BTSC stereo/SAP decoder
100TDA9610Audio FM processor for VHS
100TDA9614HAudio processor for VHS
1A10SAA7186Digital video scaler
101PCA8516Stand-alone OSD IC
111SAA7165Video enhancement D/A processor
111SAA9065Video enhancement and D/A processor
Group C (1100)
001TEA6100FM/IF for computer-controlled radio
010TEA6821/2Car radio AM
010TEA6824TCar radio IF IC
0A1A0TSA5511/2/41.3 GHz PLL frequency synthesizer for TV
0A1A0TSA5522/3M1.4 GHz PLL frequency synthesizer for TV
01A0TDA8735150 MHz PLL frequency synthesizer
01A0TSA6057Radio tuning PLL frequency synthesizer
01A0TSA6060Radio tuning PLL frequency synthesizer
01A0UMA1014Frequency synthesizer for mobile telephones
100TDA8722Negative video modulator with FM sound

Address Allocation Table Group D to F (Cont..)

GROUP(1)TYPE NUMBERDESCRIPTION
Group D (1101)
00A0TDA8043QPSK demodulator and decoder
00A0TDA9170YUV processor with picture improvement
0A1A0PCF8573Clock/calendar
A2A1A0TDA8443AYUV/RGB matrix switch
01A0TDA8745Satellite sound decoder
100TDA1551Q2 ´ 22 W BTL audio power amplifier
1A1A0TDA4845Vector processor for TV-pictures tubes
1A1A0UMA1000TData processor for mobile telephones
11A0PCD4440Voice scrambler/descrambler for mobile telephones
Group E (1110)
000PCD3316Caller-ID on Call Waiting (CIDCW) receiver
000TDA91772nd address for LTI (1st is ’40’)
000TDA91782nd address for LTI (1st is ’40’)
00A0SAA7192Digital colour space-converter
Group F (1111)
XXXReserved addresses
Group 0 to F (0000 to 1111)
XXXPCF8584I2C-bus controller




I2C  Basic Design

SDA (Serial Data Line)

This pin serves a bidirectional purpose, transferring addresses and data both into and out of the device. It is an open-drain terminal.

Hence, the SDA bus necessitates a pull-up resistor to VCC (typically 10k Ω for 100 kHz, 2 kΩ for 400 kHz). During normal data transfer, SDA can change only during SCL low, reserving alterations during SCL high specifically for indicating the Start and Stop conditions.

SCL (Serial Clock Line)

The input clock synchronizes the data transfer to and from the device. The master generates all clock pulses, including the acknowledged clock pulse.

  • Master device (Master node)
    • Node that generates the clock and initiates communication with slave
  • Slave device (Slave node)
    • Functioning as a node that receives the clock and responds exclusively when addressed by the master, this device plays a pivotal role in the I2C communication protocol.
  • The address space and the total bus capacitance of 400 pF collectively limit the maximum number of nodes.
  • Note : Basically SDA and SCL Open drain (So need Pulled up resistor)

I2C Message Protocols

I²C defines basic types of messages, each of which begins with a START and ends with a STOP:

  • Single message where a master writes data to a slave;
  • Single message where a master reads data from a slave;
  • Combined messages, where a master issues at least two reads and/or writes to one or more slaves.

Master & Salve function


I2C Physical Layer

  • Device count limit: max capacitance 400pF

I2C Pull-up resistor

Centrally suggest used Pull-up resistor for i2c communication scl and sda line is 2Kohm for 100Kbps and 10Kohm for 400Kbps. Refer this : http://www.ti.com/lit/an/slva689/slva689.pdf

I2C Minimum pull-up resistor value

  • Furthermore, determining the minimum resistance is straightforward and relies on factors such as the bus voltage (Vbus), the maximum voltage considered as a logic-low (VOL), and the maximum current that the pins can sink when at or below VOL (IOL).
  • Formula : Rp(min) = (Vbus – VOL) / IOL

I2C Minimum pull-up resistor value

  • The maximum pull-up resistance is based on the needed rise-time of the clock (dependent on the I2C clock frequency), and the total capacitance on the bus. The I2C specification (http://cache.nxp.com/documents/user_manual/UM10204.pdf) lists the maximum total bus capacitance with a pull-up resistor to be 200 pF (it can be up to 400 pF if the pull-up is a current source, section 5.1). This specification also describes the rise-time of SDA/SCL to be a maximum of 300 ns in “Fast-mode” – 400 kHz.
  • Formula : Rp(min) = rt / ( 0.8473 * C)
  • Here, rt represents the maximum allowed rise-time of the bus, and Cb denotes the total bus capacitance.

I2C Pull-up resistor Example

For Fast-mode I2C communication  with the following parameters, calculate the pullup resistor value. Cb=200pF, VCC = 3.3V,
  • Rp(Max) = tr/(0.8473*Cb) = (3000*10^-9)/(0.8473* (200*10^-12)) = 1.77kohm
  • Rp(Min) = (Vcc-Vol)/Iol = (3.3-0.4)/3*10^-3) = 966.667ohm
Therefore, we can select any available resistor value between 966.667Ω and 1.77 kΩ. The value of the pullup resistor can be selected based on the trade-off for the power consumption and speed.

I2C Data Frame

It operates in a byte-oriented transmission mode.

 

I2C Bus Characteristics

  • Initiation of data transfer is permissible only when the bus is not busy (free).
  • During data transfer, the data line must remain stable whenever the clock line is high. Interpretation of changes in the data line while the clock line is high as a Start or Stop condition takes place.
  • An Acknowledge bit must follow each byte.

I2C Bus Busy :

  • During the transition from the Start (S) to the Before (P) state, the protocol unfolds a series of critical events.

I2C Bus Free :

  • Before the Start (S) and after the Stop (P) conditions, the I2C protocol encompasses crucial states that dictate the initiation and conclusion of data transfer.
  • While both data and clock lines remain high, the system awaits the initiation of the next phase in the communication process.

I2C Start (S) Condition

  • A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.

I2C Stop (P) Condition

  • The occurrence of a low-to-high transition on the SDA line, while the clock (SCL) is high, serves as the determinant for a Stop condition. All operations must end with a Stop condition.

I2C Repeated Start (Sr) Condition

I2C Data Valid condition

  • Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device.

I2C data transfer condition

  • Data is transferred with the Most Significant Bit (MSB) first. An Acknowledge bit must follow each byte.

I2C read/write conditions

  • The last bit of the control byte holds significance as it defines the operation to be performed. Specifically, when set to ‘1,’ a read operation is selected, whereas when set to ‘0,’ a write operation is chosen.

I2c Acknowledgement (ACK) Condition

  • When a device acknowledges, it must pull down the SDA line precisely during the Acknowledge clock pulse, ensuring the SDA line remains stable-low throughout the high period of the Acknowledge-related clock pulse.
  • The master generates all clock pulses, including the acknowledged clock pulse.

I2C Not Acknowledgement (NACK) Condition


I2C Clock Synchronization

I2C Clock Stretching

If a slave is pulling the clock down, it’s called “clock-stretching” and is a signal to the master to pause until the slave is ready.

The Below diagram is raspberry bi i2c clock stretching

I2C Arbitration

  • What will happens if the two masters are write different data to same slave-1 in I2C?
  • What will happens if the two masters are write same data to same slave-1 in I2c?
  • How to know the data of master-1 or master-2 writes same data in slave-1?(conditions : if two masters are write same data to same slave-1, in I2c)
  • What will happens if the two masters are read data from same slave-1 in I2c?


I2C Single master with multi-slave connection diagram

i2C Multi-Master with Multi-Slave connection diagram


I2C LM75 Temperature Data format Example

Example 1 :

When employing the LM75 temperature sensor in its simplest mode, the master initiates the process by sending the address along with a read bit. Subsequently, it reads two bytes back. Noteworthy is that since the master transmitted the address, the slave promptly acknowledges, indicating its readiness for further communication. Then the slave sends a byte, which the master acknowledges with an ACK. Then the slave sends the second byte, to which the master responds with a NACK and a stop signal to say it’s done.

Master: Start Signal
Master: Address + Read Bit
Slave:  ACK
Slave:  First byte of data
Master: ACK
Slave:  Second / last byte of data
Master: NACK
Master: Stop Signal

Example 2 : Concluding the protocol, there are also instances of multi-part communications. For instance, if the master intends to transmit a byte to the slave and subsequently read multiple bytes, it follows a sequence. Initially, the master sends the address with a write signal and then retransmits the address with a read signal. To signify the change in mode, the master employs the “repeated start” signal, essentially a regular start signal when there has been no preceding stop. To illustrate, consider the LM75 example, where the master first signals its intention to read the high-temperature setting and subsequently reads the two bytes back.

Master: Start Signal
Master: Address + Write Bit
Slave:  ACK
Master: Set the high-temperature register for reading
Slave:  ACK
Master: (Re-) Start Signal
Master: Address + Read Bit
Slave:  ACK
Slave:  First byte of data
Master: ACK
Slave:  Second / last byte of data
Master: NACK
Master: Stop Signal

I2C Advantages & Disadvantage

Advantage

  • Only uses two wires
  • Supports multiple masters and multiple slaves
  • The ACK/NACK bit affirms the successful transfer of each frame.
  • Hardware is less complicated than with UARTs
  • Well-known and widely used protocol

Disadvantages

  • Slower data transfer rate than SPI
  • The data frame size is limited to 8 bits
  • More complicated hardware needed to implement than the SPI

Tools and Analyzer


Simulator of I2C



I2C Interface Example


Refer Websites


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