Embedded Protocol – SPI Communication

SPI is an abbreviation for Serial Peripheral Interface, which stands for Synchronous Serial Communication Interface. It is utilized for short-distance communication and was developed by Motorola in 1980, later becoming a de facto standard. SPI communication operates in full-duplex mode. It is also sometimes referred to as the Four-Wire Serial Bus (FWSB), distinguishing it from Three, Two, and One Wire Serial Bus protocols. The four-wire protocol includes SCL, SS, MISO, and MOSI. SPI operates as a single master protocol.

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Applications

• SPI Bus is commonly using for flash memory, sensor, real-time-clocks(RTC)
• This bus is commonly used to send the data between micro-controllers to smal peripherals like LCD Display, Sensors, Shift Registers, ADC.
• Typical application issecure digital card and Liquid Crystal Display system

Speed

Master only generate the clock signal. So the communication speed is depends up on master clock. Slave support various speed. Master can’t generate clock signals, it’s only synchronize with master clock signal

• Microchip’s SPI Slave MCP23S08 Supports up to 10MHz SPI™ clock speeds
• Microchip’s SPI Slave MCP23S17 Supports up to 10MHz SPI™ clock speeds

Signal Lines

• SCLK  or SCK   –    Serial Clock (Output from Master Device)
• MOSI, SIMO, SDI, DI, DIN, SI or MTSR – Master Output Slave Input (Data out from the master)
• MISO, SOMI, SDO, DO, DOUT, SO, MRST – Master Input Slave Output (Data output from the slave)
• SDIO or SIO – Serial Data I/O (Bi-Directional)
• CS, SS, SSEL, nSS, /SS, SS# –  Chip Select or Slave select (Often Active Low, output from the master)

Modes

• QIO
• DIO
• QOUT
• DOUT

Hardware

• Status
• Control
• Data register
• Shifted logic
• Baud rate generator
• Master/slave control logic
• Port control logic

block Diagram

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Master and Slave Connections

Single Master and single Salve Connection

Multi Salve and Single Master Connection

Independent slave configuration

Daisy chain configuration

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Communication Signals

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‘Clock polarity’ (CPOL) and ‘clock phase’ (CPHA).

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bit-banging

Example of bit-banging the master protocol

 Below is an example of bit-banging the SPI protocol as a master with CPOL=0, CPHA=0, and eight bits per transfer.

/*
 * Simultaneously transmit and receive a byte on the SPI.
 *
 * Polarity and phase are assumed to be both 0, i.e.:
 * - input data is captured on the rising edge of SCLK.
 * - output data is propagated on the falling edge of SCLK.
 *
 * Returns the received byte.
 */
uint8_t SPI_transfer_byte(uint8_t byte_out) {
    uint8_t byte_in = 0;
    uint8_t bit;

    for (bit = 0x80; bit; bit >>= 1) {
        /* Shift-out a bit to the MOSI line */
        write_MOSI((byte_out & bit) ? HIGH : LOW);

        /* Delay for at least the peer's setup time */
        delay(SPI_SCLK_LOW_TIME);

        /* Pull the clock line high */
        write_SCLK(HIGH);

        /* Shift-in a bit from the MISO line */
        if (read_MISO() == HIGH)
            byte_in |= bit;

        /* Delay for at least the peer's hold time */
        delay(SPI_SCLK_HIGH_TIME);

        /* Pull the clock line low */
        write_SCLK(LOW);
    }

    return byte_in;
}

This code appears to be a function SPI_transfer_byte that simultaneously transmits and receives a byte on the this bus. It follows the assumed settings of SPI, where both polarity and phase are 0. The function iterates through each bit of the byte, shifting it out on the MOSI line while shifting in data from the MISO line.

Example : Bit banking for sending a byte on an SPI bus.

// transmit byte serially, MSB first
void send_8bit_serial_data(unsigned char data) {
    int i;

    // select device (active low)
    output_low(SD_CS);

    // send bits 7..0
    for (i = 0; i < 8; i++) {
        // consider leftmost bit
        // set line high if bit is 1, low if bit is 0
        if (data & 0x80)
            output_high(SD_DI);
        else
            output_low(SD_DI);

        // pulse clock to indicate that bit value should be read
        output_low(SD_CLK);
        output_high(SD_CLK);

        // shift byte left so next bit will be leftmost
        data <<= 1;
    }

    // deselect device
    output_high(SD_CS);
}

This code appears to transmit data serially, starting with the MSB (Most Significant Bit) and shifting out each bit one by one. It sets the data output line (SD_DI) high or low based on the value of the current bit being transmitted. Then it pulses the clock line (SD_CLK) to indicate that the bit value should be read. Finally, it deselects the device by setting the chip select line (SD_CS) high.

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Advantages  & Disadvantages

Advantages	Disadvantages
Full duplex communication	Requires more pins on IC packages than I²C
Higher throughput than I²C protocol	No in-band addressing; Out-of-band chip select signals
Not limited to 8-bit words in the case of bit-transferring	No hardware flow control
Arbitrary choice of message size, contents, and purpose	No slave acknowledgment
Simple hardware interfacing	Multi-master busses are rare and awkward
Typically lower power requirements than I²C	Without a formal standard, validating conformance is not possible
No arbitration or associated failure modes	Only handles short distances compared to other standards
Slaves use the master’s clock, and don’t need precision oscillators
Transceivers are not needed
At most one “unique” bus signal per device (CS); all others are shared

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SPI Interview Questions

• https://aruneworld.com/embedded/interview-questions-spi/

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SPI Interface Example

• SPI Interface with PIC Micro-Controller : https://electrosome.com/spi-pic-microcontroller-mplab-xc8/

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Reference

• http://dlnware.com/theory/SPI-Bus
• https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
• SPI Block Guide By Motorola
• https://en.m.wikipedia.org/wiki/Bit_banging
• https://www.sanfoundry.com/iot-questions-answers-spi-protocol/
• http://www.eeherald.com/section/design-guide/esmod12.html
• Interface with following IC’s: Maxim MAX1242/3- low-power, 10-bit analog- to-digital converters (ADCs) al ADCs

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